1. Field of the Invention
The present invention relates to a high voltage transfer circuit and, more particularly, to a high voltage transfer circuit that facilitates analysis into fail of an initial product, by monitoring a high voltage generated within a chip or directly applying an external high voltage to the inside of the chip using a high voltage switch having a NMOS transistor.
2. Discussion of Related Art
In order to program, erase and read a flash memory cell, it is required that voltages depending on these operations be applied to a control gate, a source, a drain and a well, respectively. For example, in order to program the flash memory cell, a high voltage must be generated using a pumping circuit within a memory chip and the high voltage has to be applied to the control gate of the memory cell selected by a decoder. At this time, the operation of the pumping circuit is verified by monitoring whether the high voltage generated by the pumping circuit is sufficient for the operation of the cell. FIG. 1 is a circuit diagram illustrating the construction of a conventional high voltage transfer circuit for the monitoring.
FIG. 1 illustrates the conventional high voltage transfer circuit for monitoring a high voltage (VPP) generated in the pumping circuit 11, which is applied to a word line of a memory cell array 13 selected by a decoder 12. A detailed construction of the conventional high voltage transfer circuit will be described in detail with reference to FIG. 1.
A first high voltage level shifter 14 selectively outputs the high voltage (VPP) generated in the pumping circuit 11 according to a test enable signal (TESTEN). A second high voltage level shifter 15 selectively outputs a voltage of a second node Q12 that keeps the potential of a monitoring pad 16, according to the test enable signal (TESTEN). First and second PMOS transistors P11 and P12, which are serially connected between a first node Q11 being the output terminal of the pumping circuit 11 and a second node Q12 being the input terminal of the monitoring pad 16, are driven by the output signals of the first and second high voltage level shifters 14 and 15, respectively, to transfer the high voltage (VPP) to the monitoring pad 16.
FIG. 2 is a circuit diagram illustrating the construction of the high voltage level shifter used in the conventional high voltage transfer circuit shown in FIG. 1, a detail configuration of which will be described as follows:
A first PMOS transistor P21 driven by the potential of a second node Q22 is connected between the output terminal VPP of the pumping circuit 11 and a first node Q21. A first NMOS transistor N21 driven by the test enable signal (TESTEN) is connected between the first node Q21 and the ground terminal Vss. A second PMOS transistor P22 driven by the potential of the first node Q21 is connected between the output terminal VPP of the pumping circuit 11 and the second node Q22. A second NMOS transistor N22 driven by an inverse signal of the test enable signal (TESTEN) that is inverted by a first inverter 121, is connected between the second node Q22 and the ground terminal Vss. Meanwhile, the first node Q21 serves as an output terminal OUT.
In the above, if the input terminal of the monitoring pad 16 is connected in place of the output terminal VPP of the pumping circuit 11, it operates as the second high voltage level shifter.
The method of driving the first high voltage level shifter constructed above will be described below.
If the test enable signal (TESTEN) is applied as a HIGH state, the first NMOS transistor N21 is turned on and the potential of the first node Q21 maintains a LOW state. Meanwhile, the test enable signal (TESTEN) applied as the HIGH state is inverted to a LOW state through a first inverter I21. The second NMOS transistor N22 is turned off by the signal that was inverted to the LOW state. The second PMOS transistor P22 is turned on by the potential of the first node Q21 that keeps the LOW state, so that the high voltage (VPP) is applied to the second node Q22. Further, the first PMOS transistor P21 is turned off by the potential of the second node Q22 that keeps the HIGH state since the high voltage (VPP) is applied to the second node Q22. Therefore, the potential of the first node Q21 maintains the LOW state and this potential becomes a signal that is outputted through the output terminal OUT.
Meanwhile, as the second high voltage level shifter also operates in the same manner as above, it outputs a signal of a LOW state if the test enable signal (TESTEN) is applied as a HIGH state.
In the conventional high voltage transfer circuit as above, if the test enable signal (TESTEN) is applied as a HIGH state in the test mode for monitoring the high voltage generated in the pumping circuit, the first and second high voltage level shifters 12 and 13 are driven to output a signal of a LOW state. The first and second PMOS transistors P11 and P12 are thus driven to supply the high voltage (VPP) to the monitoring pad 16. Furthermore, the operation of the pumping circuit 11 is verified by measuring the high voltage (VPP) supplied to the monitoring pad 16.
Since the PMOS transistor could not transfer the high voltage of 20V or higher in view of its characteristic, however, the conventional circuit that transfers the high voltage through the PMOS transistor driven by the high voltage level shifter could not transfer the high voltage of 20V or higher that is generated within a current NAND type flash memory chip. For this reason, it is impossible to detect fail of the high voltage flash memory device. In order to make this possible, therefore, it is necessary to develop a new PMOS transistor that can withstand the high voltage of 20V or higher.